Some of the options for launch_simulation that might be of interest to you are:
Gives control back to Tcl shell for further simulation commands or for inspection of design or output.Runs simulation on the snapshot using xsim command for a pre-specifi ed simulation time.Opens up design scope window, objects window, and waveform window to monitor the simulation.Elaborates the design into simulation snapshot using xelab command.Compiles all the VHDL fi les with xvhdl.Compiles all Verilog and System Verilog fi les with xvlog.Determines the order of parsing (if requested).Determines design sources, including fi les.Launch_simulation script does the following: To select the appropriate simulator, set the property TARGET_SIMULATOR to one of XSIM, ModelSim, IES, or VCS.
FPGA SIMULATION WAVEFORM SIMULATOR
launch_simulation is the command for not just Vivado simulator but also for other integrated simulators. On running simulation, Vivado internally calls launch_simulation command to run the simulation and displays the initial result.
These simulations are more accurate but considerably slower. After synthesis and implementation, the run simulation will also let you run post-synthesis functional/timing simulation and post-implementation functional/timing simulations, respectively. This is the fastest simulation and any issue found at this stage is the easiest to fifi x. Initially (before synthesis) only RTL design is available, and simulation can be performed on it via selecting run simulation from Flow Navigator window and further selecting run behavioral simulation.
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